Serial Communications using the SCI: Overview
There are two types of serial communications modules on the HCS12 chips: the SPI module and the SCI module. The Serial Peripheral Interface (SPI) is a synchronous (clocked) module used for high-speed communications over short distances with other devices that have an SPI interface. We might use the SPI to communicate with a high-speed, high-resolution A/D converter, for instance. Because of signal degradation and critical timing issues with clock skew, the SPI is not suitable for long-distance communications. Usually the SPI is used for devices on the same printed circuit board as the microcontroller only 1 to 10 inches away.
The Serial Communications Interface (SCI) module is a relatively slow, asynchronous communication port that is widely used to communicate with other embedded systems and devices. The RS-232 interface to the Dragon-12 board, for instance, uses an SCI interface. The SCI is more widely used than the SPI, and can communicate over longer distances than the SPI. We will use the SCI module in this overview.
From a historical perspective, PCs had 2 ports in the 80’s and 90’s: parallel and serial. The SCI provides the same protocol used in the PC serial port. Today, both port types are being replaced with much faster interfaces like USB 2.0. However, the simplicity of the SCI ensures it use for a very long time in embedded applications. This port is often called UART (Universal Asynchronous Receive and Transmit).
The HCS12 chip has two SCI ports: SCI0 and SCI1. Each port physically consists of two pins: a TX pin for transmission, and an RX pin for reception. These pins are shared with Port S; whether a pin is an SCI TX/RX pin or a Port S pin depends on the configuration. By enabling the SCI RX/TX for a pin, we basically "turn off" the pin connection to Port S and "turn on" the pin connection to the TX/RX registers.
The SCI0 port is hooked up to the RS-232 interface (P1) via a MAX232A-type chip which is located underneath the LCD on the Dragon-12. When you talk to DBug12 with your PC, all the data are coming in/out of the SCI0 port via the MAX232A. The MAX232A chip alters the levels of the HCS12 SCI voltage levels to be compatible with the RS-232 standard. The SCI input/output voltages are TTL type where 0V is a logic low and +5V is a logic high. RS232 on the other hand uses negative logic where a logic high is typically around -12 V and a logic low is typically around +12 V. The MAX232A chip does all these voltage conversions for you, transforming, for instance, a +5V high output from the SCI to a -12V output on the RS232, or a +12V RS232 input to a 0V SCI input.
The SCI1 port is free and will be used in this lab. The SCI1 physical interface consists of two pins. The TXD1 pin at PS3/Pin 92 is the transmit pin for the SCI1 module - we send binary data out of this pin. The RXD1 pin at PS2/Pin 91 is the receive pin, and we read in binary data via this pin. Note that the RXD1 Pin 91 from the HCS12 chip is NOT directly connected to the PS2 header pin, but is connected via pins 1-2 of jumper J23. You MUST set the jumper to position URDX1 of jumper J23 to use the SCI1 RXD1 pin. See the Dragon-12 Schematic 3 (dragon12_3_revE.jpg) for full connection details.
The SCI configuration allows for a number of options for data transmission and reception. In the simplest configuration, ten bits are involved : a start bit (logical 0), the 8 data bits, and a stop bit (logical 1). An example transmission waveform, such as what you might see if you hooked up a logic analyzer to the TX pin, is shown below. Note that the data bits are sent lsb (bit 0) first, and msb (bit 7) last. Thus, the middle 8 bits in the pulse train below are sent in the order "10110100" in a time domain signal, corresponding to an actual data byte of $2D (%0010 1101), which is an ASCII minus " - " sign.
The data rate out of/into the SCI is determined by the baud rate, and is an essential value to consider in any SCI setup. For the NRZ-encoded waveforms of the SCI, the baud rate is the same as the bit rate, so a baud rate of 9600 corresponds to a bit rate of 9600 bits/sec. For our Dragon 12 running with a PLL controlled clock at 24 MHz, the baud rate is determined by the following formula:
SCI BAUD rate = 24,000,000/(16 x BR)
where BR is the content of the SCI1BDH/L Baud Rate Registers at addresses $00D0 and $00D1. For example, for a baud rate of 9600 (baud period ~ 100 usec) , we want a BR of about 156 = $9C, so we write $00 to SCI1BDH and $9C to SCI1BDL. Note that the baud rate is the same for transmission and reception for a given SCI port; we can't set one baud rate for transmission, and another for reception on a given port.
Also note that we must always closely match the baud rates between a transmission/reception pair of devices. If one device is transmitting at 9600 baud, the receiving device it is connected to must be configured to receive at 9600 baud. The devices don't have to transmit/receive at exactly the same baud rate - in any communication system there is an allowable mismatch. For the HCS12, there can be a 4.5% mismatch between transmitting and receiving baud rate. So, for a baud rate of 9600, the transmitter could be transmitting at a baud rate of 9816 (2.25% above 9600)and the receiver receiving at a baud rate of 9384 (2.25% below 9600), and there should still be successful communication between the devices.
The basic mechanics of serial transmission are simple: (1) we load a data register with 8 bits of data; (2) once the data register is full, the data is transferred to a shift register automatically by the hardware; (3) the data in the shift register are padded with a start/stop bit, and then shifted out on the TX pin a bit at a time at the set baud rate.
For serial reception, the basic mechanics are reversed: (1) we wait for the shift register connected to the RX pin to fill with serial data; (2) once the RX shift register is filled, the data is immediately transferred to the data register (the transfer is automatically done by the hardware); (3) we then read the data register to see what data was received.
The mechanics of SCI data transmission/reception are as follows. For transmission, we first enable the transmit register by setting the Transmit Enable (TE) bit in the SCI1CR2 Control Register at address $00D3. Once enabled, the transmitter is operational, and waiting for data to output. We then write our 8 bits of data to the SCI1 data register called SCI1DRL at address $00D7. Once we write the data to this register, the data is then immediately transferred to a shift register, where it is serially outputted one bit at a time (lsb first) at the selected baud rate from the TX pin. The Transmit Data Register Empty (TDRE) flag is set when the transmit data register is empty (because the data has been transferred to the serial shift register). We can then write new data to the SCI1DRL register for transmission. The graphic below outlines the steps noted above.
To receive data, we first enable the receive register by setting the Receive Enable (RE) bit in the SCI1CR2 Control Register at address $00D3. The RX pin is connected to a source of TTL data. The RX register waits until it sees a 1 to 0 transition signifying a start bit, and then reads data into a shift register (lsb first) in a serial fashion at the selected baud rate. In reference to the TX shift/data register graphic above, think of the received data coming in on the left side of the receive register and shifting to the right, so that the lsb then corresponds to bit 0. Thus, the bits that we read will be aligned correctly in the receive data register, with the lsb at bit 0 and the msb at bit 7.
Once the shift register is full of the received data, the data is then immediately transferred to the data register SCI1DRL at address $00D7. This will set the Register Data Register Full (RDRF) flag, indicating that we can now read the received data in register SCI1DRL at address $00D7. Once we have read our newly received data, we can then read in new data to the shift register via the RX pin. Note that we can simultaneously receive and transmit data from an HCS12, since each uses a different pin.
Note that our data register for transmission and reception has the same address: $00D7. Think of this as an address with two 8-bit slots: a transmission data slot and a received data slot. Whenever we WRITE to the address $00D7, the hardware "knows" we want to send it to the transmission slot. Whenever we READ the address $00D7, the hardware "knows" we want the received data slot. So, we can be reading/writing to the data register without the transmitted/received data interfering with each other.
From a software point of view, to use the SCI1 for simple 8 bit, non-parity communication we follow the steps below:
1. Select the baud rate via SCI1BDH/L Baud Rate Registers at addresses $00D0 and $00D1.
2. Enable transmission and/or reception as desired by setting the TE and/or RE bits in the SCI1CR2 Control Register at address $00D3.
3. For transmission, poll the TDRE flag and write data to the SCI1DRL register at address $00D7 when the TDRE flag is set. The data we write to the SCI1DRL register is the data that will be immediately output from the TX pin.
4. For reception, poll the RDRF flag. When the RDRF flag is set, we can then read in the received data by reading the SCI1DRL register at address $00D7. The data we read in from this register is that which was input via the RX pin.
We have described the most basic form of SCI serial communication above. The HCS12 can be configured for many other situations such as parity (even/odd, 7 or 8 bit), single wire RX/TX, loopback, break signals, etc. Read the HCS12 Serial Communications Interface (SCI) Block Guide for more details.
To follow on from this module, go to the SCI transmit demo which describes how to set up a Code Warrior project for data transmission using the SCI.
SCI Overview